The present invention relates to high speed bus systems. More particularly, the present invention relates to a programmable timing module which allows the effective measurement and adjustment of clock signals in a high speed bus system.
Many contemporary bus systems are synchronous in their operation. That is, bus system operations are controlled by one or more clock signals. The bus system shown in FIG. 1A is exemplary. In FIG. 1A, a master 10 is connected to a plurality of slave devices via a high speed bus. Only one connected slave device 13 is shown for the sake of clarity. Slave devices are typically connected to the bus system through a corresponding plurality of connectors (11a . . . 11n). Each connector 11 provides the mechanical and electrical means by which a module, once inserted into the connector, is operatively connected to the bus, and via the bus is connected to master 10.
Modules 13 may be memory devices, memory modules comprising a plurality of memory devices, speciality processors, transceivers, etc. Master 10 may be a microprocessor, a logic unit, a memory controller, a graphics controller, or similar control device.
The bus comprises a plurality of xe2x80x9cnxe2x80x9d signal lines which may be used to communicate control information, address information and/or data (collectively, xe2x80x9cinformationxe2x80x9d) between one or more of the modules 13 and master 10. In many high speed bus systems, the signal lines of the bus are necessarily terminated in a termination impedance 20. By carefully matching signal line impedances, information may be effectively transferred at higher speeds.
The bus further includes one or more signal lines communicating one or more clock signals. The exemplary clock signal in the following description originates at an external clock source 17 and travels down one signal line towards the master 10. This first clock signal 15 is often referred to as a Clock-To-Master (CTM). At some point, typically at master 10, CTM 15 is turned around to form a second clock signal, Clock-From-Master (CFM) 16 which travels away from master 10 down another signal line.
While a CTM/CFM set of clock signals is used to describe the present invention below, one of ordinary skill in the art will recognize that the present invention is applicable to bus systems using a single clock signal or a plurality of clock signals, whether such clock signals are internally generated within the bus system or externally generated. Further, while the exemplary CTM/CFM set of clock signals traverse the entire length of the communications channel defined by the bus, the present invention finds application in bus systems which use more localized clock signals communicated between a more limited set of bus system components.
Returning to the bus system shown in FIG. 1A, it is assumed that a plurality of modules is inserted into connectors 11b through 11n. Each one of these modules receives information from master 10 in relation to CFM 16. Similarly, each one of these modules transmits information to master 10 in relation to CTM 15. In order for the bus system to function properly, CTM 16 and CFM 15 must operate within very high tolerances. Accordingly, means are required to measure (or detect) the clock signals and, where necessary, to adjust the timing characteristics of the clock signals.
Conventionally, a special timing module is used to measure and adjust the clock signals. In their physical form, conventional timing modules are configured much like other modules 13 populating connectors 11. However, rather than transmit and receive information to/from master 10, the conventional timing module receives the clock signals from their corresponding signal lines and provides one of a group of selectable delays to the received clock signals. For example, 10, the conventional timing module may provide a clock signal delay selected from a group of delays, such as, (xe2x88x92100 ps, xe2x88x9250 ps, 0 ps, +50 ps, and +100 ps).
Once inserted into the bus system via a connector, the conventional timing module provides a test point through which a test set of test instrument may detect the actual timing characteristics of a clock signal traversing the bus, and compare the actual timing characteristics to a reference. As necessary, a fixed adjustment delay is selected from the set of possible clock signal delays and applied to the clock signal. Such measurement and adjustment are typically made by a technician during the debugging stage of the bus system""s implementation.
A number of problems are associated with the use of a conventional timing module. First, the conventional timing module occupies a connector. Channel length is an important bus system design consideration, and a full bus system configuration (i.e., a maximum number of modules per given channel length) can not be achieved when a conventional timing module occupies a connector.
Second, the conventional timing module provides a fixed, preset adjustment. No provision is made for dynamically adjusting a clock signal delay during bus system operation. If the clock signal wanders after being adjusted, or if the clock signal needs to be skewed to test the bus system timing margins, then the bus system must be shut down and a new timing module manually inserted into the channel. This repeated intervention by a technician is costly, time consuming, and prone to human error.
The present invention generally provides a timing module which is directly inserted into one or more signal lines communicating clock signals. Such an approach allows a full bus system configuration. Further, the timing module according to the present invention may adjust clock signal delay during bus system run-time, such that technician intervention, subsequent clock adjustment, and bus system re-initialization are avoided. In contrast to the conventional timing module, the timing module of the present invention allows clock signal timing margins to be further optimized electronically by the bus system master, or a separately connected controller.
Thus, in one aspect the present invention provides a bus system including a master mounted on a motherboard, and a bus comprising a plurality of signal lines traversing the motherboard and connecting the master to a plurality of connectors. Each connector is adapted to receive a module, and the plurality of signal lines includes a clock signal line communicating a clock signal within the bus system. The bus system also comprises a timing module connected to the clock signal line without use of one of the plurality of connectors, and connected to a controlling device. The timing module is adapted to receive the clock signal and adjust the clock signal in relation to a control signal from the controlling device.
In another aspect, the present invention provides a timing module in a bus system adapted to receive and adjust a clock signal, the module comprising; an I and Q generator receiving the clock signal and generating a Q signal and an I signal, wherein the Q signal and I signal are normal one to another, a first balanced modulator receiving the Q signal and a first modulation control signal, and generating a modulated Q signal in response thereto, a second balanced modulator receiving the I signal and a second modulation control signal, and generating a modulated I signal in response thereto, and a transformer circuit combining the modulated Q signal and the modulated I signal to form a phase adjusted clock signal.
In yet another aspect, the present invention provides a method of adjusting a clock signal in a bus system, wherein the bus system comprises a master connected to a plurality of connectors via a bus, each one of the connectors is adapted to receive a module, and the bus comprising a plurality of signal lines including a clock signal line communicating a clock signal, wherein the bus system further comprises a timing module connected to the clock signal line, and where the method comprising; detecting the clock signal from the clock signal line outside of any one of the plurality of connectors and generating clock signal information, communicating the clock signal information to a controlling device, comparing the clock signal information to a reference, defining a control signal in relation to the comparison, applying the control signal to the timing module to adjust the clock signal, and adjusting the clock signal in relation to the control signal.